The present invention relates to a semiconductor memory device; and, more particularly, to improvements of a semiconductor memory device in test efficiency.
As well-known in the art, a semiconductor memory device is operated by receiving addresses, commands, data, etc. from a memory controller in its actual use. Upon test of the semiconductor memory device, it is connected to test equipment and tested by taking addresses, commands, data, etc. from the test equipment in order to check if it is normally operated.
FIG. 1 is a view showing an arrangement of data pins and banks in a conventional semiconductor memory device.
In FIG. 1, there is shown an x32 semiconductor memory device which outputs data using 32 data pins DQs. An entire chip is operated in x32, including 4 memory banks operating in x8. The arrangements of memory banks and data pins DQs may differ little by little depending on semiconductor memory devices, but a general case in which one bank uses 8 data pins is shown in FIG. 1 for illustration.
For reference, memory banks are regions with regular sizes into which a storage portion of a semiconductor memory device is divided for efficient operation of data, and are composed of a plurality of memory cells.
FIG. 2 illustrates the connection between the conventional semiconductor memory devices and test equipment.
As shown in the drawing, data pins of each of the conventional semiconductor memory devices and input/output (I/O) pins of the test equipment are connected in a one-to-one fashion. Thus, if the test equipment having 256 IO pins tests x32 semiconductor memory device, it can test up to 8 chips at the same time.
In such a semiconductor memory device, it is an important issue to reduce time and costs taken for its test. For this, it is required that a small capacity test equipment can test as many as possible chips at a time.
Consequently, there is a need for a technology capable of testing a large number of chips at a time even while using the same test equipment.